Why a flip makes heat: following the electrons

Horace Hub · the bottom of the chain Why a flip makes heat: following the electrons Your note of Mon 26 Oct asked why a transistor flip releases heat, and to see the electrons move. In short: every flip charges or drains a tiny capacitor through a transistor, and the carriers crossing that transistor hand their energy to the silicon lattice. Each flip leaves ½CV² of heat, whatever the transistor. Built Tue 27 Oct 2026 (week 44) on your earlier Horace work: the Hamming ladder (E60), the one-gate runs (E61), the flow-M flip (Q124), ASAP7 in SPICE (Q126) and the transistor ledger (Q128). Every number names its file under Sources. Voltages are the minion rail's 0.517 V unless marked; SPICE numbers come from ASAP7, an open 7 nm kit, not this chip's own devices. 1 · The answer2 · The inverter3 · What else heats it4 · Inside the FMA5 · Scale6 · Could it be less?7 · Inverter in depthSources 1The supply pays CV²; half is heat at once, half on the way down Charging a node: the supply pays the whole square, the node keeps only the lower triangle Your open netlist's average toggling net, C = 2.233 fF, charged to 0.517 V. Follow the marked slice: that bit of charge left the supply at 0.517 V but landed on the node while the node sat at only 0.06 V, so almost all of its energy, the part above the diagonal (V − v), was lost on the way as heat. Charge that arrives late lands near 0.517 V and is mostly kept. The two triangles come out equal. On the fall nothing is drawn from the supply; the stored triangle drains to ground as heat. Textbook: Rabaey, ch. 5; Weste and Harris, ch. 5. Numbers: Q128 §2. A gate's output is a node with a small capacitance: the next gates' inputs plus the wire. Raising it from 0 to V takes charge Q = CV, and every bit of that charge leaves the supply at the full V, so the supply pays QV = CV². The node keeps only ½CV², because the first charge went on while it was still near 0 V. The other half is lost in the pull-up transistor on the way. When the node falls, its stored ½CV² drains to ground through the pull-down and becomes heat too. So every flip, up or down, leaves ½CV². The split doesn't depend on the transistor: a weaker one charges the node more slowly and loses exactly the same. Where it turns into heat: the field across the conducting channel speeds the carriers up, and they give that energy to the silicon lattice by scattering off it, setting the lattice vibrating (phonons). That's Joule heating. In a 7 nm transistor the channel is so short that many carriers cross it with few collisions and shed most of their energy at the drain end, mostly as optical phonons, which barely move and decay into the acoustic phonons that carry heat away (Pop, Sinha and Goodson, 2006). The wire's resistance takes its share too, in proportion to its share of the resistance on the path. 2The inverter, electron by electron New to electronics? Section 7, the inverter in depth, starts from zero: the inverter's history, the five ideas of electricity you need, the transistor as a switch, and twelve step-by-step demos. Then come back here. Each edge moves 7,206 electrons and leaves 0.298 fJ of heat; only the rise draws from the supply A CMOS inverter at 0.517 V driving your open netlist's average net. Each dot is a packet of about 300 electrons. Input 1→0 (output rises) Input 0→1 (output falls) Play Step The circuit The same edge as electron energy For an electron, ground is uphill of the rail. The node's level slides down as it charges. Early electrons fall far, late ones barely: on average half the 0.517 eV, so ½CV² per edge. Drawn from the supply 0.000 fJ Stored on the capacitor 0.000 fJ Released as heat (PMOS · NMOS) 0.000 fJ 0 of 7,206 electrons moved this edge0 electrons drawn from the supply this cycleheat: PMOS 0.000 fJ · NMOS 0.000 fJ The output is low. Press “Input 1→0” to raise it, or Play to watch both edges. electrons (a packet of ~300)holes in the PMOS channela carrier heating the latticedrawnstoredheat, PMOSheat, NMOS Meters are per cycle, reset at each rise; bars run to CV² = 0.597 fJ. Load: Q128 §2's average toggling signal net, 2.233 fF (0.485 fF transistor gates, 0.892 fF wire inside the cells, 0.856 fF wire between them). The node charges with an RC time constant, slowed tens of billions of times (the real edge takes about 20 ps); the flashes cluster at each channel's drain end. The inverter's own nodes add 0.045 fJ a cycle, 7.4% of the total (section 3). When the input falls, the p-type transistor (PMOS) conducts and the output rises. Electrons leave the node's top plate, cross to the VDD rail and enter the supply, which lifts each one by 0.517 eV and pushes one out at ground, into the capacitor's bottom plate. When the input rises, the n-type transistor (NMOS) conducts and the output falls: electrons come up from ground through the NMOS and refill the top plate. Over a full cycle electrons go ground → node → rail, the opposite way to the current arrows, as your 26 Oct fix says. Inside the PMOS the current is carried by holes, the gaps where electrons are missing, so there the hollow dots move down: the same current, as valence electrons hop up into the gaps. All the dots move together because a series loop carries one current. Real electrons drift slowly; what travels fast is the push, the way a full pipe delivers water at the far end the moment you push at the near end. 3What else heats it: three smaller sources ride on top At 0.517 V the load's CV² is 92.6% of an inverter's switch; the inverter's own share is 7.4% One INVx1 driving a 2.105 fF net, ASAP7 in SPICE at 0.517 V, per cycle (rise plus fall): 0.6077 fJ. the net's CV²: 0.5626 fJ (92.6%)the inverter's own nodes and overlap current: 0.0451 fJ (7.4%) Short circuit While the input ramps, both transistors are briefly half on and current runs straight from rail to ground. At the edges this design makes (23 ps rising, 17 ps falling), short circuit and gate-to-drain (Miller) coupling together add 1.3–3.0% to a switch. A slow 2 ns edge adds 7.5% at 0.517 V and 59% at 0.7 V. Leakage An off transistor still passes a trickle, switching or not, and it grows with temperature. One SPICE inverter leaks 0.035–0.043 nA at 0.517 V and 25 °C. For the card, your idle law is 12.6 W fixed plus a leakage term of 23.3 W at 80 °C that e-folds every 36 °C; E66 is measuring the two terms apart on aifoundry2 this morning. Glitches When a gate's inputs arrive at different times, its output can flip and flip back before it settles, and each extra edge costs ½CV² like any other. With real gate delays your multiplier tree makes 1,871 physical toggles per random multiply-add against 1,244 at zero delay, about 1.4× the energy. Sources: Q128 §1 (the stacked bar, the edge sweep, the inverter's leakage); the 21 Sep model.json idle law, as quoted in E66's registration; Q124's chip-diagram facts (glitches). No single file splits the card's watts among these, so there is no share bar for the card. Short circuit and leakage are current that never charges a node; a glitch is a real flip that nobody needed. At 0.517 V the first is small because the band of input voltage where both transistors conduct is narrower than at 0.7 V, which is why it can't explain why one flip costs more than another on this chip. 4Inside the multiply-add: one input bit sets off hundreds of flips One flipped bit of b toggles 381 wires in the multiplier, and each wire pays ½CV² Your Q124 flip, followed through one lane: bit 11 of b, with a = π, in a gate-level simulation of a netlist synthesized from the chip's RTL. 1 One bit of b flips. In this multiplier b is the multiplicand; a is the one that gets recoded. 2 Booth rows. Radix-4 Booth recoding reads a's significand three bits at a time and makes 16 rows of 33 bits, each 0, ±b or ±2b. The flipped bit of b changes a bit in every row that isn't zero. With a = π about half the rows are nonzero (9 of 16 by the recoding rule); with a = 1.0 only one or two are, one reason your quiet partner is cheaper. 3 Wallace tree. Four levels of 4:2 compressors, two full adders each, squeeze the 16 rows to two. A full adder's sum is a ⊕ b ⊕ c and its carry is the majority of the three, so a changed input always flips the sum and sometimes the carry, which moves one column left. On silicon: 248 full-adder cells, mostly the textbook 28-transistor mirror adder, plus XOR, majority and compound gates. 4 Product adder. Adds the last two rows; a change can ripple along the carry chain. 5 The rest of the seven-stage unit. Alignment, normalization, rounding and the accumulator see the changed product too. 381physical wires toggle in the multiplier (129 in stage f1, 252 in f2) 1,946named RTL signal bits change across the unit (482 distinct nets) 745 fJwhat the card pays for this flip, ± 56 (E65) Adding it up (estimates, arithmetic shown). 381 wires × 0.2985 fJ (the average net's ½CV²) ≈ 0.11 pJ. Priced from the actual cells: 0.11–0.13 pJ at zero delay, and glitches add about 40%. Against the card's 745 fJ, the multiplier's own switching is 0.11–0.13 ÷ 0.745 = 15–17% of this flip, 21–24% with glitches. Your ladder's average flip (a = 1.0) costs 116.7 fJ at the board, 87.5 fJ on the minion rail (E60). The open netlist prices the same flips at 46.3 fJ: 32.9 fJ of net switching, 32.9 ÷ 0.2985 ≈ 110 average-net toggles, plus 13.4 fJ inside the cells. That's 53% of the rail. Against one XOR: a register-file bit into one XOR costs 20.8 fJ (E60), and the XOR itself is a few percent of it (E61): most is the bit's trip from the register file. The multiply-add input bit costs 116.7 ÷ 20.8 = 5.6× more because one bit fans out into hundreds of nodes. Over a whole random multiply-add, charge onto transistor gates is 0.31 of the card's 5.78 pJ transistor gates: 0.306 pJ (5%) wire inside the cells: 0.620 pJ (11%) wire between the cells: 0.590 pJ (10%) the cells' own nodes: 0.431 pJ (7%) not in the open count: 3.84 pJ (66%) Per random fp32 multiply-add the placed open netlist makes about 4,100 net toggles: 3,623 on signal nets and 477 on the clock tree. Bottom-up it names 1.946 pJ of the card's 5.783 pJ over idle. Not yet counted: half the design's capacitance (clock-tree and repair nets added after simulation), coupling between wires, and everything outside the lane the board pays for, regulators included. Sources: Q124 facts in tensorfma32.json; Q126 open netlist; Q128 §2–3; E60; E61; E65. I started with the inverter because it's the simplest whole CMOS gate: one pull-up, one pull-down, one output node. The multiply-add's reduction tree is built from full adders instead, but every node in them is the same kind of node, charged through a pull-up network and drained through a pull-down, so each flip costs ½CV² exactly as in section 2. The multiply-add simply has hundreds of such nodes per flipped bit, and four fifths of each node's capacitance is wire. 5Scale: from Landauer's floor to the card's watts A flipped multiply-add bit sits 37 million times above Landauer's floor; the card's second, 22 powers of ten Each bar's length is the number of factors of ten above kT ln 2 at 58 °C (3.17 zJ), the die temperature your E60 and E65 runs launched at. Landauer's floor, kT ln 2 at 58 °C · physics3.17 zJ · 1× One electron crossing the 0.517 V rail · Q128 §482.8 zJ · 26× One minimum transistor's gate, heat per flip · ½ of 8.94 aJ drawn per rise · Q128 §14.47 aJ · 1,410× An inverter's own switching, no load, per edge · SPICE · Q128 §112 aJ · 3,800× An inverter switching an average net (2.105 fF), per edge · SPICE · Q128 §10.30 fJ · 9.6 × 10⁴ A register-file bit flipped into one XOR · board · E6020.8 fJ · 6.6 × 10⁶ A flipped fp32 multiply-add input bit, a = 1.0 · board · E60116.7 fJ · 3.7 × 10⁷ One random fp32 multiply-add, over idle · board · E38/E39 via Q128 §35.78 pJ · 1.8 × 10⁹ One second of the card on a random fp32 matmul, 9.18 TFLOPS · 63.40 W · 21 Sep63.4 J · 2.0 × 10²² 1×10⁵×10¹⁰×10¹⁵×10²⁰× Single-edge rungs are heat per edge (½CV²); "drawn per rise" figures